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controllers:ctucanfd [2019/01/24 15:00] – [CTU CAN FD Core] pavelpisacontrollers:ctucanfd [2020/10/21 23:54] – [CTU CAN FD Core] - Intel Cyclone V DE0-Nano-SoC pavelpisa
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 ===== CTU CAN FD Core ===== ===== CTU CAN FD Core =====
 +Open-source CAN FD core
 +
 +The Czech Technical University (CTU) in Prague has developed an open-source CAN FD core and appropriate development tools. The core complies with ISO 11898-1:2015. The IP core is available under MIT license conditions. The basic features include a RX first-in, first-out (Fifo) buffer of 32 words to 4 096 words equivalent to one to 204 CAN FD data frames and four TX buffers for one CAN FD data frame each. Time stamping of frames is supported as well as time-triggered transmission of data frames.
 +
 The VHDL open-source CAN FD core project. The VHDL open-source CAN FD core project.
  
-Project pages: https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core +[[https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core | Project pages:]] Documentation and testing:
-Documentation and testing:+
   * [[http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/Progdokum.pdf | CTU CAN FD Core Component Documentation]]   * [[http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/Progdokum.pdf | CTU CAN FD Core Component Documentation]]
   * [[http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/coverage/ | The Core coverage by included test framework]]   * [[http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/coverage/ | The Core coverage by included test framework]]
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   * Integration with Intel EP4CGX15 based DB4CGX15 PCIe board   * Integration with Intel EP4CGX15 based DB4CGX15 PCIe board
     https://gitlab.fel.cvut.cz/canbus/pcie-ctu_can_fd     https://gitlab.fel.cvut.cz/canbus/pcie-ctu_can_fd
 +
 +  * Integration with Intel Cyclone V 5CSEMA4U23C6 based DE0-Nano-SoC Terasic board.
 +    https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd
  
 ===== OpenCores SJA-1000 FD Tol ===== ===== OpenCores SJA-1000 FD Tol =====

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