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| can_physical_layer:main [2016/08/12 12:34] – [CAN Transceivers] cia | can_physical_layer:main [2016/11/07 17:40] – [CAN Transceivers] heinz |
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| The question: "Are there any compatibility problems with using a mixed 3.3V and 5V transceiver network?" was answered by Steve Corrigan s-corrigan1@ti.com: "I have a bus with 30 3.3-V HVD230s and 30 5-V 82C250s and have no problems." | The question: "Are there any compatibility problems with using a mixed 3.3V and 5V transceiver network?" was answered by Steve Corrigan s-corrigan1@ti.com: "I have a bus with 30 3.3-V HVD230s and 30 5-V 82C250s and have no problems." |
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| | Nowadays all micro controllers don't work anymore with 5V but 3.3V. To get ideas for the CAN bus transceiver designs in 3.3 V system read [[http://e2e.ti.com/blogs_/b/analogwire/archive/2016/10/18/top-five-reasons-to-use-3-3v-can-transceivers?hootPostID=f9f0ef82804f6aae5ea5cc1cad5be478 | Top five reasons to use 3.3V CAN transceivers]]. |
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| Some of the transceivers, e.g. NXP TJA1041, try to detect own problems by a feature called DOMINANT CLAMPING DETECTION. With this feature they introduce a low bit rate limit: TJA1041 Chapter TXD DOMINANT CLAMPING DETECTION: ..... The tdom(TXD) timer defines the minimum possible bit rate of 40 kbit/s. Other namings are **Dominant Timeout**.\\ The dominant time-out circuit prevents the driver from blocking network communications if a local CAN controller fault occurs. The time-out circuit is triggered by a falling edge on TXD. If no rising edge occurs on TXD before the time-out of the circuits expires, the driver is disabled to prevent the local node from continuously transmitting a dominant bit. If a rising edge occurs on TXD, commanding a recessive bit, the timer will be reset and the driver will be re-enabled. The time-out value is set so that normal CAN communication will not cause the dominant time-out circuit to expire. | Some of the transceivers, e.g. NXP TJA1041, try to detect own problems by a feature called DOMINANT CLAMPING DETECTION. With this feature they introduce a low bit rate limit: TJA1041 Chapter TXD DOMINANT CLAMPING DETECTION: ..... The tdom(TXD) timer defines the minimum possible bit rate of 40 kbit/s. Other namings are **Dominant Timeout**.\\ The dominant time-out circuit prevents the driver from blocking network communications if a local CAN controller fault occurs. The time-out circuit is triggered by a falling edge on TXD. If no rising edge occurs on TXD before the time-out of the circuits expires, the driver is disabled to prevent the local node from continuously transmitting a dominant bit. If a rising edge occurs on TXD, commanding a recessive bit, the timer will be reset and the driver will be re-enabled. The time-out value is set so that normal CAN communication will not cause the dominant time-out circuit to expire. |
