| Both sides previous revisionPrevious revisionNext revision | Previous revisionLast revisionBoth sides next revision |
| controllers:arasan [2015/07/31 11:06] – [FPGA / IP] heinz | controllers:arasan [2022/07/04 11:28] – [FPGA / IP] heinz |
|---|
| ===== FPGA / IP ====== | ===== FPGA / IP ====== |
| |
| [[http://arasan.com/products/can-fd/ | CAN FD]] The CAN controller IP implements the ISO11898 (CAN2.0A, CAN2.0B) as well as newer high performance **Non ISO CAN-FD** protocols. It can be integrated into devices that require CAN connectivity commonly used in automotive and industrial applications. The ISO 11898-2.2015 version is planned for end of 2015. The IP provides an AHB-Lite slave interface for connecting to the CPU with the option of APB and it supports a 32-bit interface. | |
| Provided as [[wp>Verilog]] HDL | |
| | Arasan [[https://www.arasan.com/news/arasan-announces-its-2nd-generation-of-can-ip/ | announces]] its 2’nd Generation of CAN IP on May 2022. |
| | The [[https://www.arasan.com/products/can-fd/ | CAN controller IP]] implements the ISO11898 (CAN2.0A, CAN2.0B) as well as TT-CAN, CAN-FD (ISO 11898-1.2015, plus earlier ISO, and Non-ISO Bosch specifications).It can be easily integrated with the host processor using standard AMBA AHB/AXI interfaces. The highly configurable controller core supports programmable Interrupts, data and baud rates, acceptance filters & flexible buffering schemes allows it to be fine-tuned to the specific need for the application. |
| | The defense and aerospace sectors in addition to automotive are a major target market for Arasan’s fault tolerant CAN IP. |
| | |
| | |
| | |
| | [[http://arasan.com/products/can-fd/ | CAN FD]] The [[https://www.arasan.com/products/can-fd/ | CAN controller IP]] implements the ISO11898 (CAN2.0A, CAN2.0B) as well as newer high performance **Non ISO CAN-FD** protocols. It is compliant with ISO 11898-1:2015 DIS. |
| | The IP can be integrated into devices that require CAN connectivity commonly used in automotive and industrial applications. The ISO 11898-2.2015 version is planned for end of 2015. The IP provides an AHB-Lite slave interface for connecting to the CPU with the option of APB and it supports a 32-bit interface. |
| | Provided as [[wp>Verilog]] HDL. |
| | |
| | Currently data sheet is available available only after registration. |
| |
| ===== 8 bit Controllers ===== | ===== 8 bit Controllers ===== |
