Welcome to the CAN-bus Wiki project

CTU - Czech Technical University in Prague

There are many CAN bus related project implemented at the Faculty of Electrical Engineering of the Czech Technical University in Prague

CTU CAN FD

CTU CAN FD is a soft IP core whose development started at Czech Technical University. The core is usable in FPGA and ASIC implementations. It supports ISO and NON-ISO versions of CAN FD protocol and it is compliant with ISO 11898-1 2015. The core is open-source, see the licensing conditions on project page.

HW Features:

  • 2 - 8 TX buffers
  • FIFO-like RX buffer with configurable size
  • HW filtering of RX frames
  • Time-stamping (RX) and Time-triggered transmission (TX)
  • Variety of interrupts
  • Listen only mode, Restricted operation mode, Self test mode, Test Mode,
  • Support of ASIC manufacturing testability (DFT and memory testing)

Project pages:

Documentation and testing:

Integration with FPGA SoCs and boards:

  • Integration with Zynq-7000 system

https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top

  • Integration with Intel EP4CGX15 based DB4CGX15 PCIe board

https://gitlab.fel.cvut.cz/canbus/pcie-ctu_can_fd

  • Integration with Intel Cyclone V 5CSEMA4U23C6 based DE0-Nano-SoC Terasic board.

https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd

Apart from core itself, there are several sub-projects:

Usage:

OpenCores SJA-1000 FD Tol

OpenCores SJA-1000 controller modified to ignore CAN FD frames which allows it to coexists and send frames on network with CAN FD traffic. The core is packed as a Xilinx Vivado component.

Project pages: https://gitlab.fel.cvut.cz/canbus/zynq/sja1000-fdtol


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