Welcome to the CAN-bus Wiki project

Microsemi

Try to put the latest devices on top of each section and mark end-of-line products. Only specify the main parameters of the micro controllers and go more into deep with details about the CAN interface. Always try to put a link to the data sheet or manual.

SoC

SmartFusion2 166 MHz ARM Cortex-M3 Processor and Microcontroller Subsystem in SmartFusion2 SoC FPGA Devices. Microsemi has announced the availability of its first production-qualified System-on-Chip FPGAs, the M2S050 and M2S050T, for June 2013.

The SmartFusion2 concept is used in HMS new flagship, the NP40 network processor. It is used by HMS to realize standard fieldbus protocols like CAN, but also all kinds of real time Ethernet.

CAN Controller Features:

Possibly the Inicore CANmodule-IIIx is implemented. Press release.

Receive Path

  • 32 receive buffers
  • Each buffer has its own message filter
  • Message filter covers: ID, IDE, RTR, Data byte 1, and Data byte 2
  • Message buffers can be linked together to build a bigger message array.
  • Automatic remote transmission request (RTR) response handler with optional generation of RTR interrupt

Transmit Path

  • 32 Transmit message holding registers with programmable priority arbitration
  • Message abort command
  • Single-shot transmission (SST) (no automatic retransmission upon error or arbitration loss) EDAC

The User Manual Chapter 11 – CAN Controller.

FPGA

Microsemi (USA) has announced PCIe implementations based on IGLOO2 FPGAs. The products, which are compliant to PCI express specifications, also provide CAN connectivity. The on-chip CAN has been tested by the C&S group (Germany) according to ISO 16845 and some additional test cases.

8 bit Controllers

16 bit Controllers

32 bit Controllers

DSPs

Stand alone CAN Controllers


QR Code
QR Code controllers:microsemi (generated for current page)